1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to an integrated circuit having a plurality of boundary-scan test circuits connected in a series-linked boundary test scan chain to allow individual portions of the integrated circuit to be individually manipulated and configured.
2. History of the Prior Art
As integrated circuits have become physically smaller while including more and more individual elements, it has become more difficult to test those circuits. In order to assure that such circuits may be tested accurately without inordinate expense, these integrated circuits have been equipped with circuitry adapted to allow boundary-scan testing. Boundary-scan testing uses a plurality of shift register stages built into each integrated circuit. A boundary-scan controller circuit in each integrated circuit controls the transfer of data serially from an input port to an output port through the stages of the boundary-scan shift register and allows use of the data so that circuit testing may be conducted from external terminals without the need for probes and other imprecise instruments. Boundary-scan testing makes the test process for integrated circuits so equipped faster and more accurate.
An industry standard has been implemented for boundary-scan test circuits so that integrated circuits from different manufacturers may be connected in a serial chain within an electronic system. This standard is described in an industry specification, IEEE JTAG 1149.1 ("the Standard"). The Standard provides a protocol by which various test functions may be accomplished through specified test ports defined by the specification. Essentially, the Standard outlines the details of the serial path of linked test registers (called a boundary-scan register chain) through each integrated circuit and defines the properties of the controller for each integrated circuit. The linked serial path of the boundary-scan register chain allows data to be transferred to various test and other registers within any of the integrated circuits. From these registers, various operations may be conducted by the controllers with the specific integrated circuits.
Boundary-scan test circuits offer a number of advantages beyond the ability to rapidly test integrated circuitry. Because it is useful in conducting tests of integrated circuits to read and write to the integrated circuits, one of the operations which it is possible to perform using boundary scan circuitry is writing to memory cells in memory arrays with which the boundary scan circuitry is associated. This offers special advantages with certain circuits. For example, certain memory devices may be placed in a particular condition by writing to the devices. Often the condition of memory devices is used to determine logic operations to be accomplished by associated circuitry. In such a case, such memory devices may be test programmed using the boundary scan circuitry in order to determine the accuracy of a program to be installed to control operations of the associated circuits. For example, certain field programmable gate arrays include various logic circuits which function according to conditions which may be written to static random access memory (SRAM) cells. By varying the conditions of the SRAM cells, different selectable logic functions are provided. Typically, such field programmable gate arrays include other non-volatile memory arrays (in addition to the SRAM cells) such as EPROM or flash EEPROM arrays which provide long term storage for the conditions which are written to the SRAM cells when power is applied to the gate array. These non-volatile memory arrays are not programmed until a correct program providing the desired logic functions has been ascertained because the non-volatile devices, once programmed, cannot be reprogrammed without removal from the system.
Because of the facility to write to memory cells using the boundary scan circuitry, it has become possible to trial program the SRAM devices of such a gate array until correct operation of the logic devices is obtained and then program the non-volatile memory devices with the correct conditions for writing to the SRAM array.
Using prior art boundary scan circuitry, it has been necessary to vary the condition of the memory devices of the SRAM and non-volatile memory arrays to obtain working programs to control the logic operations of the arrays before the field programmable arrays are placed into use. Recently, it has become apparent that it would be very useful if portions of field programmable logic devices could be programmed dynamically so that portions of the logic could be changed in response to changes encountered during operation of the circuitry. In fact, it is desirable to be able to reconfigure portions of a field programmable logic device in response to operation occurring in other operating portions of the field programmable logic device. Prior art boundary scan circuitry cannot conveniently be utilized for this purpose because it is only able to deal with each integrated circuit as a whole.